Documents dont l'auteur est "Yang, Jie"

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Nombre de documents: 5

Auteur ou autrice

Li, T., Liao, Z., Zhang, C., Yang, J., & Sawan, M. (décembre 2025). A Neuromorphic FPGA-Based Architecture for Energy-Efficient Visual Recognition [Communication écrite]. 37th International Conference on Microelectronics (ICM 2025), Cairo, Egypt (6 pages). Lien externe

Tian, F., Shao, K., Zheng, J., Liu, Z., Wu, H., Liao, Z., He, J., Guan, X., Dong, P., Fang, C., Shen, Z., Zhao, S., Yang, J., Sawan, M., Tsui, C.-Y., & Tim Cheng, K.-T. (novembre 2025). Lemem: A 179.8TFLOPS/W, 24.21TFLOPS Learning-In-Memory Processor with Layer-Fused Forward/Backward Pipeline for Edge DNN/SNN Training/Inference [Communication écrite]. Asian Solid-State Circuits Conference (A-SSCC 2025), Daejeon, Korea, Republic of. Lien externe

Liao, Z., Li, T., Shen, Z., Fang, C., Yang, J., & Sawan, M. (octobre 2025). NeuroPlat: An FPGA-Based Neuromorphic Computing Platform with Optimized Toolchain for Efficient SNN Deployment [Communication écrite]. International Conference on Machine Intelligence and Nature-Inspired Computing (MIND 2025), Xiamen, China. Lien externe

Ye, Y., Mao, Y., Zou, W., Wu, H., Liu, X., Tan, Z., Katebi, M., Yang, J., & Sawan, M. (octobre 2025). A Reconfigurable 8-Channel Dual-Mode Neural Stimulator with High-Voltage Compliance and 97% Efficiency [Communication écrite]. Asia Pacific Conference on Circuits and Systems (APCCAS 2025), Busan, Korea, Republic of (4 pages). Lien externe

Liao, Z., Li, T., Shen, Z., Fang, C., Yang, J., & Sawan, M. (octobre 2025). A Pipeline-Driven FPGA Accelerator with Memory-Scheduling for Neuromorphic Computing [Communication écrite]. Asia Pacific Conference on Circuits and Systems (APCCAS 2025), Busan, Korea, Republic of (5 pages). Lien externe

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