Documents dont l'auteur est "Le Beux, Sébastien"

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Nombre de documents: 23

Destras, O., Le Beux, S., Göhring de Magalhães, F., & Nicolescu, G. (2024). Survey on activation functions for optical neural networks. ACM Computing Surveys, 56(2), 35 (30 pages). Disponible

Wang, Y., Aouina, A., Li, H., O' Connor, I., Nicolescu, G., & Le Beux, S. (2019). Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(3), 742-746. Lien externe

Nikdast, M., Nicolescu, G., Le Beux, S., & Xu, J. (édit.) (2017). Photonic interconnects for computing systems: Understanding and pushing design challenges. Lien externe

Duong, L. H. K., Wang, Z., Nikdast, M., Xu, J., Yang, P., Wang, Z., Wang, Z., Maeda, R. K. V., Li, H., Wang, X., Le Beux, S., & Thonnart, Y. (2016). Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(7), 2475-2487. Lien externe

Li, H., Fourmigue, A., Le Beux, S., O'Connor, I., & Nicolescu, G. (mars 2016). A thermal-Aware Laser Tuning Approach for Silicon Photonic Interconnects [Communication écrite]. 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop 2016), Dresden, Germany. Non disponible

Li, H., Fourmigue, A., Le Beux, S., O'Connor, I., & Nicolescu, G. (2016). Towards Maximum Energy Efficiency in Nanophotonic Interconnects with Thermal-Aware On-Chip Laser Tuning. IEEE Transactions on Emerging Topics in Computing, 6(3), 343-356. Lien externe

Duong, L. H. K., Nikdast, M., Xu, J., Wang, Z., Thonnart, Y., Le Beux, S., Yang, P., Wu, X., & Wang, Z. (mars 2015). Coherent crosstalk noise analyses in ring-based optical interconnects [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2015), Grenoble, France. Lien externe

Hui, L., Le Beux, S., Nicolescu, G., & O'Connor, I. (janvier 2015). Energy-efficient optical crossbars on chip with multi-layer deposited silicon [Communication écrite]. 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba, Japan. Lien externe

Hui, L., Fourmigue, A., Le Beux, S., Letartre, X., O'Connor, I., & Nicolescu, G. (mars 2015). Thermal aware design method for VCSEL-based on-chip optical interconnect [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2015), Grenoble, France. Lien externe

Duong, L. H. K., Xu, J., Wu, X., Wang, Z., Yang, P., Le Beux, S., & Nikdast, M. (2014). A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip. IEEE Design & Test, 31(5), 55-65. Lien externe

Le Beux, S., Li, H., O'Connor, I., Cheshmi, K., Liu, X., Trajkovic, J., & Nicolescu, G. (mars 2014). Chameleon: Channel efficient optical network-on-chip [Communication écrite]. 17th Design, Automation and Test in Europe (DATE 2014), Dresden, Germany. Lien externe

Le Beux, S., Li, H., Nicolescu, G., Trajkovic, J., & O'Connor, I. (2014). Optical crossbars on chip, a comparative study based on worst-case losses. Concurrency Computation Practice and Experience, 26(15), 2492-2503. Lien externe

Le Beux, S., Li, H., Nicolescu, G., & O'Connor, I. (mai 2014). A reconfigurable optical network on chip for streaming applications [Communication écrite]. 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC 2014), Montpellier, France (2 pages). Lien externe

Le Beux, S., O'Connor, I., Li, Z., Letartre, X., Monat, C., Trajkovic, J., & Nicolescu, G. (mai 2013). Potential and pitfalls of silicon photonics computing and interconnect [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, China. Lien externe

Le Beux, S., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2013). Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocessors and Microsystems, 37(1), 87-98. Lien externe

Le Beux, S., Moss, L., Marquet, P., & Dekeyser, J.-L. (2011). A high level synthesis flow using model driven engineering. Dans Algorithm-Architecture Matching for Signal and Image Processing - Best Papers from Design and Architectures for Signal and Image Processing 2007 and 2008 and 2009 (Vol. 73, p. 253-274). Lien externe

Le Beux, S., Trajkovic, J., O'Connor, I., & Nicolescu, G. (octobre 2011). Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC) [Communication écrite]. 19th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2011), Kowloon, Hong kong. Lien externe

Gamatie, A., Le Beux, S., Piel, E., Atitallah, R. B., Etien, A., Marquet, P., & Dekeyser, J.-L. (2011). A model-driven design framework for massively parallel embedded systems. Transactions on Embedded Computing Systems, 10(4), 1-36. Lien externe

Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (mars 2011). Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology [Communication écrite]. 14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France. Lien externe

Le Beux, S., Bois, G., Nicolescu, G., Bouchebaba, Y., Langevin, M., & Paulin, P. (2010). Combining mapping and partitioning exploration for NoC-based embedded systems. Journal of Systems Architecture, 56(7), 223-232. Lien externe

Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2010). Multi-optical network-on-chip for large scale MPSoC. IEEE Embedded Systems Letters, 2(3), 77-80. Lien externe

Le Beux, S., Nicolescu, G., Bois, G., & Paulin, P. (mai 2010). A system-level exploration flow for optical network on chip (ONoC) in 3D MPSoC [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. Lien externe

Le Beux, S., Nicolescu, G., Bois, G., Bouchebaba, Y., Langevin, M., & Paulin, P. (juillet 2009). Optimizing configuration and application mapping for MPSoC architectures [Communication écrite]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2009), San Francisco, California. Lien externe

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