 | Up a level |
Collaboration networkThis graph maps the connections between all the collaborators of {}'s publications listed on this page.
Each link represents a collaboration on the same publication. The thickness of the link represents the number of collaborations.
Use the mouse wheel or scroll gestures to zoom into the graph.
You can click on the nodes and links to highlight them and move the nodes by dragging them.
Hold down the "Ctrl" key or the "⌘" key while clicking on the nodes to open the list of this person's publications.
Word cloudA word cloud is a visual representation of the most frequently used words in a text or a set of texts. The words appear in different sizes, with the size of each word being proportional to its frequency of occurrence in the text. The more frequently a word is used, the larger it appears in the word cloud. This technique allows for a quick visualization of the most important themes and concepts in a text.
In the context of this page, the word cloud was generated from the publications of the author {}. The words in this cloud come from the titles, abstracts, and keywords of the author's articles and research papers. By analyzing this word cloud, you can get an overview of the most recurring and significant topics and research areas in the author's work.
The word cloud is a useful tool for identifying trends and main themes in a corpus of texts, thus facilitating the understanding and analysis of content in a visual and intuitive way.
Daigneault, M.-A., & David, J. P. (2015, May). Intermediate-level synthesis of a Gauss-Jordan elimination linear solver [Paper]. 29th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015), Hyderabad, India. External link
Daigneault, M.-A., & David, J. P. (2013, February). Hardware description and synthesis of control-intensive reconfigurable dataflow architectures [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, Calif.. External link
Daigneault, M.-A., & David, J. P. (2013, April). High-level description and synthesis of floating-point accumulators on FPGA [Paper]. 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Seattle, WA, United states. External link
Daigneault, M.-A., & David, J. P. (2012, August). Raising the abstraction level of HDL for control-dominant applications [Paper]. 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), Oslo, Norway. External link
Daigneault, M.-A., & David, J. P. Synchronized-Transfer-Level Design Methodology Applied to Hardware Matrix Multiplication [Paper]. International Conference on Reconfigurable Computing and Fpgas (Reconfig 2012), Cancun, Mexico (7 pages). External link
Daigneault, M.-A., Langlois, J. M. P., & David, J. P. (2008, October). Application Specific Instruction set processor specialized for block motion estimation [Paper]. IEEE International Conference on Computer Design (ICCD 2008), Lake Tahoe, CA. External link
Bergeron, É., Feeley, M., Daigneault, M.-A., & David, J. P. (2008, June). Using dynamic reconfiguration to implement high-resolution programmable Delays on an FPGA [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec. External link
Daigneault, M.-A., & David, J. P. (2010, February). Towards 5ps resolution TDC on a dynamically reconfigurable FPGA [Abstract]. 8th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, California. External link
Daigneault, M.-A. (2009). Utilisation de la reconfiguration dynamique des FPGA pour le contrôle précis et exact des délais dans les convertisseurs temps à numérique [Master's thesis, École Polytechnique de Montréal]. Available
Daigneault, M.-A. (2015). Synthèse et description de circuits numériques au niveau des transferts synchronisés par les données [Ph.D. thesis, École Polytechnique de Montréal]. Available
