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Daigneault, M.-A. (2015). Synthèse et description de circuits numériques au niveau des transferts synchronisés par les données [Ph.D. thesis, École Polytechnique de Montréal]. Available
Daigneault, M.-A., & David, J. P. (2015, May). Intermediate-level synthesis of a Gauss-Jordan elimination linear solver [Paper]. 29th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015), Hyderabad, India. External link
Daigneault, M.-A., & David, J. P. (2013, February). Hardware description and synthesis of control-intensive reconfigurable dataflow architectures [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, Calif.. External link
Daigneault, M.-A., & David, J. P. (2013, April). High-level description and synthesis of floating-point accumulators on FPGA [Paper]. 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Seattle, WA, United states. External link
Daigneault, M.-A., & David, J. P. (2012, August). Raising the abstraction level of HDL for control-dominant applications [Paper]. 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), Oslo, Norway. External link
Daigneault, M.-A., & David, J. P. Synchronized-Transfer-Level Design Methodology Applied to Hardware Matrix Multiplication [Paper]. International Conference on Reconfigurable Computing and Fpgas (Reconfig 2012), Cancun, Mexico (7 pages). External link
Daigneault, M.-A., & David, J. P. (2010, February). Towards 5ps resolution TDC on a dynamically reconfigurable FPGA [Abstract]. 8th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, California. External link
Daigneault, M.-A. (2009). Utilisation de la reconfiguration dynamique des FPGA pour le contrôle précis et exact des délais dans les convertisseurs temps à numérique [Master's thesis, École Polytechnique de Montréal]. Available
Daigneault, M.-A., Langlois, J. M. P., & David, J. P. (2008, October). Application Specific Instruction set processor specialized for block motion estimation [Paper]. IEEE International Conference on Computer Design (ICCD 2008), Lake Tahoe, CA. External link
Bergeron, É., Feeley, M., Daigneault, M.-A., & David, J. P. (2008, June). Using dynamic reconfiguration to implement high-resolution programmable Delays on an FPGA [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec. External link
