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Anwar, H., Chao, C., & Beltrame, G. (juin 2015). A probabilistically analysable cache implementation on FPGA [Communication écrite]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). Lien externe
Chao, C., Panerati, J., Hafnaoui, I., & Beltrame, G. (juin 2017). Static probabilistic timing analysis with a permanent fault detection mechanism [Communication écrite]. 12th IEEE International Symposium on Industrial Embedded Systems (SIES 2017), Toulouse, France (10 pages). Lien externe
Chao, C., Panerati, J., & Beltrame, G. (septembre 2016). Effects of online fault detection mechanisms on Probabilistic Timing Analysis [Communication écrite]. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2016), Connecticut. Lien externe