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Documents dont l'auteur est "Abuelnasr, Ahmed"

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Aller à : 2025 | 2024 | 2023 | 2021 | 2020
Nombre de documents: 13

2025

Abdelfatah, M. M. S., Abuelnasr, A., Amer, M., Savaria, Y., & Hassan, A. (juin 2025). A Comparative Analysis of Off-Policy DRL Strategies for Analog Circuit Optimization: A Case Study on Bandgap References [Communication écrite]. 23rd IEEE Interregional NEWCAS Conference (NEWCAS 2025), Paris, France. Lien externe

Altoobaji, I., Abuelnasr, A., Amer, M., Ali, M., Audet, Y., & Hassan, A. (juin 2025). A Tunable and Area-Efficient Delayed Fault Detection Circuit for Voltage Monitoring Systems with 10.19% Voltage Sensitivity [Communication écrite]. 23rd IEEE Interregional NEWCAS Conference (NEWCAS 2025), Paris, France. Lien externe

2024

Amer, M., Abuelnasr, A., Ali, M., Hassan, A., Trigui, A., Ragab, A., Sawan, M., & Savaria, Y. (2024). Enhanced dynamic regulation in Buck Converters: integrating input-voltage feedforward with voltage-mode feedback. IEEE Access, 12, 7310-7328. Disponible

Abuelnasr, A. (2024). System-On-Chip Design Acceleration Using Simulation-Based Optimization and Causal Discovery [Thèse de doctorat, Polytechnique Montréal]. Disponible

Abdelfatah, M. M. S., Novshadian, M., Abuelnasr, A., & Hassan, A. (novembre 2024). Attention-Based Dynamic Channel-Wise Pruning of Neural Networks with Knowledge Distillation Fine-Tuning [Communication écrite]. 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2024), Nancy, France. Lien externe

Abuelnasr, A., Ragab, A., Amer, M., Gosselin, B., & Savaria, Y. (2024). Incremental reinforcement learning for multi-objective analog circuit design acceleration. Engineering Applications of Artificial Intelligence, 129, 107426 (18 pages). Lien externe

2023

Abuelnasr, A., Amer, M., Ali, M., Hassan, A., Gosselin, B., Ragab, A. R. A., & Savaria, Y. (2023). Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers. IEEE Transactions on Circuits and Systems I: Regular Papers, 70(4), 1555-1565. Disponible

Amer, M., Abuelnasr, A., Hassan, A., Ragab, A., Sawan, M., & Savaria, Y. (2023). A Half-bridge Gate Driver with Self-adjusting and Tunable Dead-time Modes for Efficient Switched-mode Power Systems. IEEE Transactions on Power Electronics, 15 pages. Lien externe

2021

Abuelnasr, A., Amer, M., Ragab, A., Gosselin, B., & Savaria, Y. (mai 2021). Causal information prediction for analog circuit design using variable selection methods based on machine learning [Communication écrite]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). Lien externe

Amer, M., Abuelnasr, A., Ragab, A., Hassan, A., Ali, M., Gosselin, B., Sawan, M., & Savaria, Y. (mai 2021). Design and analysis of combined input-voltage feedforward and PI controllers for the buck converter [Communication écrite]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). Lien externe

2020

Karimi, M., Ali, M., Hassan, A., Weber-Boisvert, G., Abuelnasr, A., Sawan, M., & Gosselin, B. (juin 2020). A 1.99-ns 0.5-pJ wide frequency range level shifter with closed-loop negative feedback [Communication écrite]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Qc, Canada. Lien externe

Amer, M., Ali, M., Abuelnasr, A., Hassan, A., Nabavi, M., Savaria, Y., & Sawan, M. (juin 2020). Fully integrated dual-channel gate driver and area efficient pid compensator for surge tolerant power sensor interface [Communication écrite]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Qc, Canada. Lien externe

Abuelnasr, A., Ali, M., Amer, M., Nabavi, M., Hassan, A., Gosselin, B., & Savaria, Y. (octobre 2020). Self-Adjusting Deadtime Generator for High-Efficiency High-Voltage Switched-Mode Power Amplifiers [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2020), Sevilla, Spain (5 pages). Lien externe

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