Wissam Marrouche, Rana Farah and Haidar M. Harmanani
Article (2018)
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| Department: | Department of Computer Engineering and Software Engineering |
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| PolyPublie URL: | https://publications.polymtl.ca/61470/ |
| Journal Title: | International Journal of Computational Intelligence and Applications (vol. 17, no. 02) |
| Publisher: | Imperial College Press |
| DOI: | 10.1142/s1469026818500104 |
| Official URL: | https://doi.org/10.1142/s1469026818500104 |
| Date Deposited: | 18 Dec 2024 14:31 |
| Last Modified: | 18 Dec 2024 14:31 |
| Cite in APA 7: | Marrouche, W., Farah, R., & Harmanani, H. M. (2018). A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules. International Journal of Computational Intelligence and Applications, 17(02), -1850010. https://doi.org/10.1142/s1469026818500104 |
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