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Items where Author is "Harmanani, Haidar M."

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Marrouche, W., Farah, R., & Harmanani, H. M. (2018). A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules. International Journal of Computational Intelligence and Applications, 17(02), -1850010. External link

Marrouche, W., Farah, R., & Harmanani, H. M. (2017, April). A multiobjective optimization method for the SOC test time, TAM, and power optimization using a strength Pareto evolutionary algorithm [Paper]. 14th International Conference on Information Technology: New Generations (ITNG 2017), Las Vegas, Nevada. External link

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