A 9.2-ns to 1-μs digitally controlled multituned deadtime optimization for efficient GaN HEMT power converters

This paper presents a tunable new deadtime control circuit providing an optimal delay for power converter optimization. Our method can reduce the deadtime loss while improving the efficiency and power density of a given power converter. The circuit presents a reconfigurable delay element to generate a wide range of deadtime for different power conversion applications with varying loads and input voltages. The optimal deadtime equation for buck converters is derived, and its dependency on the input voltage and load is discussed. Experimental results show that the presented circuit can provide a wide range of deadtime delays, ranging from 9.2 ns to 1000 ns. The power consumption of the presented circuit is measured for different capacitive loads (CL) and operating frequencies ( f s). The circuit consumed a power between 610 µW and 850 µW across the measured deadtime ranges while CL = 12 pF, Vdd = 3.3 V, and fs = 200 kHz. The proposed deadtime generator can operate up to 18 MHz when the minimum deadtime of 9.2 ns is selected. The presented circuit occupies an area of 150µ m × 260µm. The fabricated chip is connected to a buck converter to validate the operation of the proposed circuit. The efficiency of a typical buck converter with minimum TDLH and optimal TDHL at ILoad = 25 mA is improved by 12% compared to a converter with a fixed deadtime of TDLH = TDHL = 12 ns.

Mots clés

Power converters; gate driver; GaN HEMT transistors; optimized deadtime control; efficiency; adjustable circuit; power consumption; load variation; different input voltage