Master's thesis (1998)
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| Additional Information: | Nom historique du département: Département de génie électrique et de génie informatique |
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| Department: |
Department of Electrical Engineering Department of Computer Engineering and Software Engineering |
| Academic/Research Directors: |
Yvon Savaria
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| PolyPublie URL: | https://publications.polymtl.ca/29441/ |
| Institution: | École Polytechnique de Montréal |
| Date Deposited: | 18 Apr 2023 15:23 |
| Last Modified: | 18 Apr 2023 15:23 |
| Cite in APA 7: | Patenaude, S. (1998). Modélisation de pannes dans les circuits logiques bipolaires en mode courant et méthodes de test adaptées [Master's thesis, École Polytechnique de Montréal]. |
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