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Abbasmollaei, M., Ould-Bachir, T., & Savaria, Y. (2025). HLSCAM: Fine-tuned HLS-based content addressable memory implementation for packet processing on FPGA. Electronics, 14(9), 1765 (22 pages). Disponible
Abbasmollaei, M., Ould-Bachir, T., & Savaria, Y. (2025). P4THLS: A Templated HLS Framework to Automate Efficient Mapping of P4 Data-Plane Applications to FPGAs. IEEE Access. Lien externe
Abbasmollaei, M., Ould-Bachir, T., & Savaria, Y. (2025). A Stateful Extension to P4THLS for Advanced Telemetry and Flow Control. Future Internet, 17(11), 530 (21 pages). Lien externe
Allabadi, A., Mahseredjian, J., Dennetière, S., Abusalah, A., Kocar, I., & Ould-Bachir, T. (2025). Acceleration strategies for EMT Simulation of HVDC systems. Electric Power Systems Research, 252, 112399 (6 pages). Lien externe
Hajizadeh, F., Bisson, P.-A., Ould-Bachir, T., & David, J. P. (juin 2025). Improved High-Radix Carry-Save Adders for Low-Latency Vector Reduction on FPGA [Communication écrite]. 23rd IEEE Interregional NEWCAS Conference (NEWCAS 2025), Paris, France. Lien externe
Hajizadeh, F., Masoom, A., Ould-Bachir, T., & David, J. P. (2025). FPGA-based simulation of grid-tied converters using frequency-dependent network equivalent. Electric Power Systems Research, 252, 112400. Présentée à International Conference on Power Systems Transients (IPST 2025), Guadalajara, Mexico. Lien externe
Hajizadeh, F., Ould-Bachir, T., & David, J. P. (2025). Enhancing CuFP library with self-alignment technique. Computers, 14(4), 118 (22 pages). Disponible
Robert, T., Ould-Bachir, T., Combet, V., & Monthéard, R. (juillet 2025). Simulation en temps-réel d'un convertisseur résonant CLLLC sur cible FPGA à bas coût [Communication écrite]. Symposium de génie électrique (SGE 2025), Toulouse, France (5 pages). Lien externe
Zamanidoost, Y., Rivron, M., Ould-Bachir, T., & Martel, S. (2025). DA OMS-CNN: Dual-Attention OMS-CNN with 3D Swin Transformer for Early-Stage Lung Cancer Detection. Informatics, 12(3), 65-65. Lien externe
