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Benacer, I. (2019). Fast, Scalable, and Flexible C++ Hardware Architectures for Network Data Plane Queuing and Traffic Management [Thèse de doctorat, Polytechnique Montréal]. Disponible
Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). A high-speed, scalable, and programmable traffic manager architecture for flow-based networking. IEEE Access, 7, 2231-2243. Disponible
Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). HPQS: A fast, high-capacity, hybrid priority queuing system for high-speed networking devices. IEEE Access, 7, 130672-130684. Disponible
