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Hamad, G. B., Ait Mohamed, O., & Savaria, Y. (2017). Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits. Journal of Electronic Testing: Theory and Applications, 33(5), 607-620. Lien externe
Hoque, K. A., Ait Mohamed, O., & Savaria, Y. (2017). Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications. Journal of Applied Logic, 25(47-68), 47-68. Lien externe
Kazma, G., Bany Hamad, G., Ait Mohamed, O., & Savaria, Y. (juin 2017). Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe
