Documents publiés en "1992"

Article de revue

Dagenais, M., Gaiotti, S., & Rumin, N. (1992). Transistor-level estimation of worst-case delays in MOS VLSI circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(3), 384-395. Lien externe

Communication écrite

Belabbes, N., Guterman, A., Savaria, Y., & Dagenais, M. (mai 1992). Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. Lien externe