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Documents dont l'auteur est "Shen, Ziyang"

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Nombre de documents: 4

Fang, C., Shen, Z., Tian, F., Yang, J., & Sawan, M. (mai 2025). An Area-Efficient and Bit-Width Configurable Carry-Save Adder Tree for Spiking Transformers [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2025), London, United Kingdom. Lien externe

Tian, F., Chen, J., Shao, K., Liu, Z., Zheng, J., Wu, H., Fang, C., Wang, X., Shen, Z., Dong, P., Yao, Y., Wang, X., Yang, J., Sawan, M., Tsui, C.-Y., & Cheng, K.-T. (avril 2025). E-NPU: A 34~126nJ/Class Event-Driven Adaptive Neural SoC with Signal-Dynamics-Aware Feature Clustering and Multi-Model In-Memory Inference/Training for Personalized Medical Wearables [Communication écrite]. IEEE Custom Integrated Circuits Conference (CICC 2025), Boston, MA, USA. Lien externe

Fang, C., Shen, Z., Zhao, S., Wang, C., Tian, F., Yang, J., & Sawan, M. (avril 2024). A 0.078 pJ/SOP Unstructured Sparsity-Aware Spiking Attention/Convolution Processor with 3D Compute Array [Communication écrite]. IEEE Custom Integrated Circuits Conference (CICC 2024), Denver, CO, USA. Lien externe

Fang, C., Shen, Z., Wang, Z., Wang, C., Zhao, S., Tian, F., Yang, J., & Sawan, M. (2024). An Energy-Efficient Unstructured Sparsity-Aware Deep SNN Accelerator With 3-D Computation Array. IEEE Journal of Solid-State Circuits, 1-13. Lien externe

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