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Sahnoun, M. , Bettayeb, B., Bassetto, S., & Tollenaere, M. (2014). Simulation-based optimization of sampling plans to reduce inspections while mastering the risk exposure in semiconductor manufacturing. Journal of Intelligent Manufacturing, 27(6), 1335-1349. Lien externe
Sahnoun, M. , Vialletelle, P., Bassetto, S., Tollenaere, M., & Bastoini, S. (novembre 2010). Historical wafer-at-risk construction in STMicroelectronics 300mm wafer fab in crollesoptimizing return on inspection through defectivity smart skipping [Communication écrite]. Manufacturing Challenges in European Semiconductor Fabs, Rousset, France. Non disponible
