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Items where Author is "Luinaud, Thomas"

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Number of items: 9.

Article

Luinaud, T., Langlois, J. M. P., & Savaria, Y. (2022). Symbolic analysis for data plane programs specialization. ACM Transactions on Architecture and Code Optimization, 20(1), 1-21. External link

Paper

Su, M., David, J. P., Savaria, Y., Pontikakis, B., & Luinaud, T. (2022, May). An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA. External link

Luinaud, T., Santiago da Silva, J., Langlois, J. M. P., & Savaria, Y. (2021, February). Design Principles for Packet Deparsers on FPGAs [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2021) (7 pages). Available

Luinaud, T., Stimpfling, T., Santiago da Silva, J., Savaria, Y., & Langlois, J. M. P. (2020, May). Bridging the gap: FPGAs as programmable switches [Paper]. 21st IEEE International Conference on High Performance Switching and Routing (HPSR 2020) (7 pages). External link

Luinaud, T., Stimpfling, T., Santiago Da Silva, J., Savaria, Y., & Langlois, J. M. P. (2020, February). Unleashing the Power of FPGAs as Programmable Switches [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020), Seaside, CA, USA (1 page). External link

Luinaud, T., Savaria, Y., & Langlois, J. M. P. (2017, May). An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search [Paper]. Great Lakes Symposium on VLSI (GLSVLSI 2017), Banff, Alberta. External link

Luinaud, T., Savaria, Y., & Langlois, J. M. P. (2017, February). An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only) [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017), Monterey, California. External link

Master's thesis

Luinaud, T. (2017). Algorithmes et architectures pour l'implémentation de la détection d'expressions régulières [Master's thesis, École Polytechnique de Montréal]. Available

Ph.D. thesis

Luinaud, T. (2022). Optimisation de la compilation de déparseurs pour processeurs réseau implémentés sur FPGA [Ph.D. thesis, Polytechnique Montréal]. Available

List generated on: Thu Dec 5 08:56:07 2024 EST