 | Monter d'un niveau |
Hamad, G. B., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (2015). Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits. Microelectronics Reliability, 55(1), 238-250. Lien externe
Hamad, G. B., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (août 2014). Modeling, analyzing, and abstracting single event transient propagation at gate level [Communication écrite]. IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS 2014), College Station, TX, USA. Lien externe
Hasan, S. R., Belanger, N., Savaria, Y., & Ahmad, M. O. (2011). All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. Integration, the VLSI Journal, 44(1), 22-38. Lien externe
Hasan, S. R., Belanger, N., Savaria, Y., & Ahmad, M. O. (2010). Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(8), 2020-2031. Lien externe
Hasan, S. R., Belanger, N., Savaria, Y., & Ahmad, M. O. (2010). Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(10), 2696-707. Lien externe
Hasan, S. R., Belanger, N., & Savaria, Y. (octobre 2008). All-digital skew-tolerant interfacing method for systems with rational frequency ratios among multiple clock domains: leveraging a priori timing information [Communication écrite]. 1st Microsystems and Nanoelectronics Research Conference. Lien externe
Hasan, S. R., & Savaria, Y. (août 2007). Metastability tolerant mesochronous synchronization [Communication écrite]. 50th Midwest Symposium on Circuits and Systems (MWSCAS 2007), Montreal, QC, Canada. Lien externe
Thibeault, C., Hariri, Y., Hasan, S. R., Hobeika, C., Savaria, Y., Audet, Y., & Tazi, F. Z. (2013). A library-based early soft error sensitivity analysis technique for SRAM-based FPGA design. Journal of Electronic Testing: Theory and Applications, 29(4), 457-471. Lien externe
