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Fiorentino, M., Thibeault, C., & Savaria, Y. (2021). Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow. IET Computers & Digital Techniques, 15(6), 409-426. Available
Fiorentino, M. (2020). Architectural Exploration of KeyRing Self-Timed Processors [Ph.D. thesis, Polytechnique Montréal]. Available
Fiorentino, M., Thibeault, C., Savaria, Y., Gagnon, F., Awad, T., Morrissey, D., & Laurence, M. (2019, May). AnARM: a 28nm energy efficient ARM processor based on Octasic asynchronous technology [Paper]. 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan. External link
Fiorentino, M., Savaria, Y., & Thibeault, C. (2017, June). FPGA implementation of Token-based Self-timed processors: A case study [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. External link
Fiorentino, M., Savaria, Y., Thibeault, C., & Gervais, P. (2016, May). A practical design method for prototyping self-timed processors using FPGAs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. External link
Fiorentino, M., Al-Terkawi, O., Savaria, Y., & Thibeault, C. (2015, June). Self-timed circuits FPGA implementation flow [Paper]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). External link
Nadal, J., Fiorentino, M., Dupraz, E., & Leduc-Primeau, F. (2020, June). A Deeply Pipelined, Highly Parallel and Flexible LDPC Decoder [Paper]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, QC, Canada. External link
