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Ardakani, A., Condo, C., Ahmadi, M., & Gross, W. J. (2018). An architecture to accelerate convolution in deep neural networks. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(4), 1349-1362. External link
Condo, C., Giard, P., Leduc-Primeau, F., Sarkis, G., & Gross, W. J. (2018). A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(4), 1420-1431. External link
Condo, C., Leduc-Primeau, F., Sarkis, G., Giard, P., & Gross, W. J. (2016, December). Stall pattern avoidance in polynomial product codes [Paper]. IEEE Global Conference on Signal and Information Processing (GlobalSIP 2016), Washington, D.C.. External link
