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Chabini, N., Aboulhamid, E. M., Chabini, I., & Savaria, Y. (2005). Scheduling and Optimal Register Placement for Synchronous Circuits Derived Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 10(2), 187-204. External link
Chabini, N., Aboulhamid, E. M., Chabini, I., & Savaria, Y. Minimizing the Number of Phases in Clocked Digital Designs Derived Using Modulo Scheduling Techniques [Paper]. Icm 2002: 14th International Conference on Microelectronics. External link
Chabini, N., Aboulhamid, M., & Savaria, Y. (2001, January). Determining schedules for reducing power consuption using mulyiple supply voltages [Paper]. International Conference on Computer Design (ICCD 2001), Austin, Texas. External link
Chabini, N., Aboulhamid, M., & Savaria, Y. (2001, January). Efficient methods for reducing register and phase requirements for synchronous circuits derived using software pipeling techniques [Paper]. European Conference on Circuit Theory and Design, Espoo, Finland. Unavailable
Chabini, N., Aboulhamid, E. M., & Savaria, Y. (2001, January). Fast method for determining an efficient bound on the optimal solution of the cost-to-time ratio problem [Paper]. 5th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001) and 7th International Conference in Information Systems Analysis and Synthesis (ISAS 2001), Orlando, Floride. Unavailable
Chabini, N., & Savaria, Y. (2001, January). Methods for optimizating register placement in synchronous circuits derived using software pipelining techniques [Paper]. 14th International Symposium on System Synthesis (ISSS 2001), Montréal, Québec. External link
Chabini, N., Aboulhamid, E. M., & Savaria, Y. (2001, January). Minimizing registe requirements for synchronous circuits derived using software pipelining techniques [Paper]. 13th International Conference on Microelectronics (ICM 2001), Rabat, Maroc. External link
Chabini, N., Aboulhamid, E. M., & Savaria, Y. (2001, April). Reducing register and phase requirements for synchronous circuits derived using software pipelining techniques [Paper]. IEEE Computer Society Workshop on VLSI (WVLSI 2001), Orlando, FL, United states. External link
Chabini, N., Bennour, I. E., Aboulhamid, E. M., & Savaria, Y. (1998, January). Static method for system performance estimation [Paper]. 10th International Conference on Microelectronics. External link
Gao, S., Al-Khalili, D., Chabini, N., & Langlois, J. M. P. (2012). Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Computers and Digital Techniques, 6(6), 372-83. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2007, July). FPGA-based efficient design approach for large-size two's complement squarers [Paper]. IEEE International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2007). Optimised Realisations of Large Integer Multipliers and Squarers Using Embedded Blocks. IET Computers and Digital Techniques, 1(1), 9-16. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, September). Efficient FPGA-based realization of complex squarer and complex conjugate using embedded mulitpliers [Paper]. IEEE International SOC Conference (SOCC 2006), Austin, TX, USA. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, June). Efficient realization of large integers multipliers and squarers [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, March). An optimized design approach for squaring large integers using embedded hardwired multipliers [Paper]. ACS/IEEE International Conference on Computer Systems and Applications. External link
