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Bensalem, H., Blaquiere, Y., & Savaria, Y. (mai 2021). Acceleration of the secure hash algorithm-256 (SHA-256) on an FPGA-CPU cluster using OpenCL [Communication écrite]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). Lien externe
Berrima, S., Blaquiere, Y., & Savaria, Y. (2021). Ring-Oscillator Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. IEEE Transactions on Instrumentation and Measurement, 70, 1-10. Lien externe
Berrima, S., Blaquiere, Y., & Savaria, Y. (2020). Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. IET Circuits Devices & Systems, 14(8), 1243-1252. Lien externe
Bensalem, H., Blaquiere, Y., & Savaria, Y. (2020). In-FPGA instrumentation framework for openCL-based designs. IEEE Access, 8, 212979-212994. Disponible
Bensalem, H., Blaquiere, Y., & Savaria, Y. (mai 2019). Toward in-system monitoring of OpenCL-based designs on FPGA [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). Lien externe
Blaquiere, Y., Basile-Bellavance, Y., Berrima, S., & Savaria, Y. (juin 2014). Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, VIC, Australia (4 pages). Lien externe
Bougataya, M., Berriah, O., Lakhssassi, A., Dahmane, A.-O., Blaquiere, Y., Savaria, Y., Norman, R., & Prytula, R. (décembre 2010). Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit [Communication écrite]. 17th IEEE International Conference on Electronics, Circuits and Systems, Athens, Greece. Lien externe
Blaquiere, Y., Savaria, Y., & El Fouladi, J. (décembre 2007). Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os [Communication écrite]. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco (4 pages). Lien externe
Blaquiere, Y., & Savaria, Y. (1987). Area Overhead Analysis of SEF: A Design Methodology for Tolerating SEU. IEEE Transactions on Nuclear Science, 34(6), 1481-1486. Lien externe
Darvishi, M., Audet, Y., Blaquiere, Y., Thibeault, C., & Pichette, S. (2019). On the susceptibility of SRAM-Based FPGA routing network to delay changes induced by ionizing radiation. IEEE Transactions on Nuclear Science, 66(3), 643-654. Lien externe
Darvishi, M., Audet, Y., Blaquiere, Y., Thibeault, C., Pichette, S., & Tazi, F. Z. (2014). Circuit level modeling of extra combinational delays in SRAM-based FPGAs due to transient ionizing radiation. IEEE Transactions on Nuclear Science, 61(6), 3535-3542. Lien externe
Guillemot, M., Nguyen, H., Bougataya, M., Blaquiere, Y., Lakhssassi, A., Shields, M., & Savaria, Y. (2016). Wafer-scale rapid electronic systems prototyping platform: User support tools and thermo-mechanical validation. Dans Novel Advances in Microsystems Technologies and Their Applications (67-100). Lien externe
Hussain, W., Fakhoury, H., Desgreys, P., Blaquiere, Y., & Savaria, Y. (2016). An asynchronous delta-modulator based A/D converter for an electronic system prototyping platform. IEEE Transactions on Circuits and Systems I: Regular Papers, 63(6), 751-762. Lien externe
Hussain, W., Savaria, Y., & Blaquiere, Y. (mai 2016). A compact spatially configurable differential input stage for a field programmable interconnection network [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. Lien externe
Hussain, W., Valorge, O., Blaquiere, Y., & Savaria, Y. (2016). A novel spatially configurable differential interface for an electronic system prototyping platform. Integration, the VLSI Journal, 55, 129-137. Lien externe
Hussain, W., Blaquiere, Y., & Savaria, Y. (2015). An interface for open-drain bidirectional communication in field programmable interconnection networks. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(10), 2465-2475. Lien externe
Laflamme-Mayer, N., Kowarzyk, G., Blaquiere, Y., Savaria, Y., & Sawan, M. (2018). A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(2), 304-315. Lien externe
Laflamme-Mayer, N., Blaquiere, Y., & Sawan, M. (2015). A configurable analog buffer dedicated to a wafer-scale prototyping platform. Analog Integrated Circuits and Signal Processing, 82(1), 57-66. Lien externe
Laflamme-Mayer, N., Blaquiere, Y., Savaria, Y., & Sawan, M. (2014). A configurable multi-rail power and I/O pad applied to wafer-scale systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(11), 3135-3144. Lien externe
Laflamme-Mayer, N., Sawan, M., & Blaquiere, Y. (février 2013). A configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems [Communication écrite]. 4th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2013), Cusco, Peru. Lien externe
Laflamme-Mayer, N., Andre, W., Valorge, O., Blaquiere, Y., & Sawan, M. (2013). Configurable input-output power pad for wafer-scale microelectronic systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(11), 2024-2033. Lien externe
Valorge, O., Blaquiere, Y., & Savaria, Y. (décembre 2010). A spatially reconfigurable fast differential interface for a wafer scale configurable platform [Communication écrite]. 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2010), Athens, Greece. Lien externe
