<  Back to the Polytechnique Montréal portal

Items where Author is "Bélanger, N."

Up a level
Export as [feed] Atom [feed] RSS 1.0 [feed] RSS 2.0
Jump to: A | B | I | K | M
Number of items: 7.

A

Alizadeh, R., Bélanger, N., Savaria, Y., & Frigon, J.-F. (2015, June). DPDK and MKL; enabling technologies for near deterministic cloud-based signal processing [Paper]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). External link

Abdollahifakhr, H., Bélanger, N., Savaria, Y., & Gagnon, F. (2015, June). Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum [Paper]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). External link

B

Bélanger, N., Antaki, B., & Savaria, Y. (1997, July). An algorithm for fast array transfers [Paper]. 11th Annual International Symposium on High Performance Computing Systems, Winnipeg, Man., Canada. Unavailable

Bélanger, N., Haccoun, D., & Savaria, Y. (1994). A multiprocessor architecture for multiple path stack sequential decoders. IEEE Transactions on Communications, 42(2-4, pt.2), 951-957. External link

I

Ioachim, I., Desrosiers, J., Soumis, F., & Bélanger, N. (1999). Fleet Assignment and Routing With Schedule Synchronization Constraints. European Journal of Operational Research, 119(1), 75-90. External link

K

Kowarzyk, G., Bélanger, N., & Savaria, Y. (2011, December). A GPGPU-based software implementation of the PBDI deinterlacing algorithm [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link

M

Mbaye, M., Bélanger, N., Savaria, Y., & Pierre, S. (2005, May). Application Specific Instruction-Set Processor Generation for Video Processing Based on Loop Optimization [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. External link

List generated on: Sun May 19 17:10:00 2024 EDT