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Alizadeh, R., Bélanger, N., Savaria, Y., & Frigon, J.-F. (juin 2015). DPDK and MKL; enabling technologies for near deterministic cloud-based signal processing [Communication écrite]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). Lien externe
Abdollahifakhr, H., Bélanger, N., Savaria, Y., & Gagnon, F. (juin 2015). Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum [Communication écrite]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). Lien externe
Kowarzyk, G., Bélanger, N., & Savaria, Y. (décembre 2011). A GPGPU-based software implementation of the PBDI deinterlacing algorithm [Communication écrite]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. Lien externe
Mbaye, M., Bélanger, N., Savaria, Y., & Pierre, S. (mai 2005). Application Specific Instruction-Set Processor Generation for Video Processing Based on Loop Optimization [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Ioachim, I., Desrosiers, J., Soumis, F., & Bélanger, N. (1999). Fleet Assignment and Routing With Schedule Synchronization Constraints. European Journal of Operational Research, 119(1), 75-90. Lien externe
Bélanger, N., Antaki, B., & Savaria, Y. (juillet 1997). An algorithm for fast array transfers [Communication écrite]. 11th Annual International Symposium on High Performance Computing Systems, Winnipeg, Man., Canada. Non disponible
Bélanger, N., Haccoun, D., & Savaria, Y. (1994). A multiprocessor architecture for multiple path stack sequential decoders. IEEE Transactions on Communications, 42(2-4, pt.2), 951-957. Lien externe
