Inter-step PWM interpolation for real-time FPGA simulation: a 1 MHz buck converter case study

The global electrification of transport, energy, and industry is driving the widespread deployment of power converters. To maximise power density and minimise passive component size, switching frequencies are moving well beyond 100 kHz. FPGAs have become the platform of choice for real-time HIL simulation of such converters. However, the pursuit of eversmaller simulation time steps leads to narrow fixed-point word lengths, accuracy issues, and beating effects. This paper proposes an inter-step PWM interpolation method that breaks this race to the bottom: by resolving the PWM switching instant to 4 ns within each 200 ns simulation step via linear state interpolation, the beating effect is suppressed. The methodology is described and implemented on the NOA Arch 1 open FPGA platform (Zynq UltraScale+, 125 MSPS I/O) and validated on a 1 MHz synchronous buck converter equipped with a reinforcementlearning- optimised controller. The proposed approach allows using a 50× larger time step than the 4 ns implementation, relaxing the timing closure constraints associated with the latter’s narrow fixed-point word length, while achieving equivalent PWM resolution and simulation accuracy.