<  Back to the Polytechnique Montréal portal

A power efficient decoder for 2GHz, 6-bit CMOS Flash-ADC architecture

S. M. Ali, R. Raut and Mohamad Sawan

Paper (2005)

An external link is available for this item
Department: Department of Electrical Engineering
PolyPublie URL: https://publications.polymtl.ca/24469/
Conference Title: 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005)
Conference Date(s): 2005-07-20 - 2005-07-24
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/iwsoc.2005.22
Official URL: https://doi.org/10.1109/iwsoc.2005.22
Date Deposited: 18 Apr 2023 15:18
Last Modified: 25 Sep 2024 16:04
Cite in APA 7: Ali, S. M., Raut, R., & Sawan, M. (2005, July). A power efficient decoder for 2GHz, 6-bit CMOS Flash-ADC architecture [Paper]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005). https://doi.org/10.1109/iwsoc.2005.22

Statistics

Dimensions

Repository Staff Only

View Item View Item