<  Back to the Polytechnique Montréal portal

A 0.18 µm CMOS multilayer and low resistive load architecture dedicated for LoC applications

Mohamed Amine Miled and Mohamad Sawan

Paper (2013)

An external link is available for this item
Department: Department of Electrical Engineering
Research Center: GR2M - Microelectronics and Microsystems Research Group
ISBN: 9781479906208
PolyPublie URL: https://publications.polymtl.ca/13424/
Conference Title: 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013)
Conference Location: Paris, France
Conference Date(s): 2013-06-16 - 2013-06-19
Publisher: IEEE
DOI: 10.1109/newcas.2013.6573668
Official URL: https://doi.org/10.1109/newcas.2013.6573668
Date Deposited: 18 Apr 2023 15:09
Last Modified: 08 Apr 2025 12:20
Cite in APA 7: Miled, M. A., & Sawan, M. (2013, June). A 0.18 µm CMOS multilayer and low resistive load architecture dedicated for LoC applications [Paper]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. https://doi.org/10.1109/newcas.2013.6573668

Statistics

Dimensions

Repository Staff Only

View Item View Item