Documents publiés en "2018"

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Benacer, I., Boyer, F.-R., & Savaria, Y. (mai 2018). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages). Lien externe

Benacer, I., Boyer, F.-R., & Savaria, Y. (2018). A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 1939-1952. Lien externe