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Bois, G. (octobre 2013). A Complete HW/SW Codesign flow for heterogeneous platforms [Communication écrite]. Workshop on Many-Core Embedded Systems (MCES2013), Montréal, Québec. Non disponible
Bois, G. (avril 2013). End-to-end automated HW/SW co-design for reconfigurable SoC [Communication écrite]. Electronic Design Process Symposium (EDPS 2013), Monterey, Calif.. Non disponible
Le Beux, S., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2013). Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocessors and Microsystems, 37(1), 87-98. Lien externe
Savard, J., Bao, L., Bois, G., & Boland, J.-F. (septembre 2013). Model-based design flow driven by integrated modular avionic simulations [Communication écrite]. SAE AeroTech Congress and Exhibition (AEROTECH 2013), Montréal, Québec. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (2013). Customised soft processor design: A compromise between architecture description languages and parameterisable processors. IET Computers and Digital Techniques, 7(3), 122-131. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (2013). Enhanced precision analysis for accuracy-aware bit-width optimization using affine arithmetic. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(12), 1853-1865. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (mai 2013). Finite-precision error modeling using affine arithmetic [Communication écrite]. 38th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2013), Vancouver, BC, Canada. Lien externe
