 | Monter d'un niveau |
Daigneault, M., & David, J. P. (juin 2010). A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA [Communication écrite]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. Lien externe
Daigneault, M.-A., & David, J. P. (février 2010). Towards 5ps resolution TDC on a dynamically reconfigurable FPGA [Résumé]. 8th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, California. Lien externe
Ould-Bachir, T., & David, J. P. (septembre 2010). FPGA-Based Real-Time Simulation of State-Space Models using Floating-Point Cores [Communication écrite]. 14th International Power Electronics and Motion Control Conference (EPE/PEMC 2010), Ohrid, Republic of Macedonia. Lien externe
Ould-Bachir, T., & David, J. P. (mai 2010). Performing floating-point Accumulation on a Modern FPGA in Single and Double Precision [Communication écrite]. 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), Charlotte, North Carolina. Lien externe
Ould-Bachir, T., David, J. P., Dufour, C., & Bélanger, J. (novembre 2010). Effective FPGA-based electric motor modeling with floating-point cores [Communication écrite]. 36th Annual Conference of IEEE Industrial Electronics (IECON 2010), Glendale, Arizona, USA. Lien externe
