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Campi, F., Toma, M., Lodi, A., Cappelli, A., Canegallo, R., & Guerrieri, R. (2003, February). A VLIW processor with reconfigurable instruction set for embedded applications [Paper]. IEEE International Solid-State Circuits Conference (ISSCC 2003), San Francisco, CA, USA. External link
Lodi, A., Chiesa, C., Campi, F., & Toma, M. (2003, May). A flexible LUT-based carry chain for FPGAs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand. External link
Lodi, A., Ciccarelli, L., Cappelli, A., Campi, F., & Toma, M. (2003, February). Decoder-based multi-context interconnect architecture [Paper]. IEEE Computer Society Annual Symposium on VLSI: New Trends and Technologies for Vlsi Systems Design (ISVLSI 2003), Tampa, FL, United states. External link
Lodi, A., Toma, M., & Campi, F. (2003, February). A pipelined configurable gate array for embedded processors [Paper]. 11th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2003), Monterey, CA, United states. External link
Lodi, A., Toma, M., Campi, F., Cappelli, A., Canegallo, R., & Guerrieri, R. (2003). A VLIW processor with reconfigurable instruction set for embedded applications. IEEE Journal of Solid-State Circuits, 38(11), 1876-1886. External link
Mucci, C., Chiesa, C., Lodi, A., Toma, M., & Campi, F. (2003, November). A C-based algorithm development flow for a reconfigurable processor architecture [Paper]. 5th International Symposium on System-on-Chip (SoC 2003), Tampere, Finland. External link
