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Campi, F., Toma, M., Lodi, A., Cappelli, A., Canegallo, R., & Guerrieri, R. (février 2003). A VLIW processor with reconfigurable instruction set for embedded applications [Communication écrite]. IEEE International Solid-State Circuits Conference (ISSCC 2003), San Francisco, CA, USA. Lien externe
Lodi, A., Chiesa, C., Campi, F., & Toma, M. (mai 2003). A flexible LUT-based carry chain for FPGAs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand. Lien externe
Lodi, A., Ciccarelli, L., Cappelli, A., Campi, F., & Toma, M. (février 2003). Decoder-based multi-context interconnect architecture [Communication écrite]. IEEE Computer Society Annual Symposium on VLSI: New Trends and Technologies for Vlsi Systems Design (ISVLSI 2003), Tampa, FL, United states. Lien externe
Lodi, A., Toma, M., & Campi, F. (février 2003). A pipelined configurable gate array for embedded processors [Communication écrite]. 11th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2003), Monterey, CA, United states. Lien externe
Lodi, A., Toma, M., Campi, F., Cappelli, A., Canegallo, R., & Guerrieri, R. (2003). A VLIW processor with reconfigurable instruction set for embedded applications. IEEE Journal of Solid-State Circuits, 38(11), 1876-1886. Lien externe
Mucci, C., Chiesa, C., Lodi, A., Toma, M., & Campi, F. (novembre 2003). A C-based algorithm development flow for a reconfigurable processor architecture [Communication écrite]. 5th International Symposium on System-on-Chip (SoC 2003), Tampere, Finland. Lien externe
