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Cesario, W. O., Nicolescu, G., Gauthier, L., Lyonnard, D., & Jerraya, A.-A. (2001). Colif: A design representation for application-specific multiprocessor SOCs. IEEE Design & Test of Computers, 18(5), 8-20. Lien externe
Cesario, W. O., Nicolescu, G., Gauthier, L., Lyonnard, D., & Jerraya, A.-A. (juin 2001). Colif: A multilevel design representation for application-specific multiprocessor system-on-chip design [Communication écrite]. International Workshop on Rapid System Prototyping (RSP 2001), Monterey, CA, USA. Lien externe
Gerin, P., Yoo, S., Nicolescu, G., & Jerraya, A.-A. (février 2001). Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures [Communication écrite]. Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan. Lien externe
Svarstad, K., Ben-Fredj, N., Nicolescu, G., & Jerraya, A.-A. (février 2001). A higher level system communication model for object-oriented specification and design of embedded systems [Communication écrite]. Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan. Lien externe
Yoo, S., Nicolescu, G., Gauthier, L., & Jerraya, A.-A. (novembre 2001). Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication [Communication écrite]. 6th International High-Level Design Validation and Test Workshop, Monterey, CA, USA. Lien externe
Yoo, S., Nicolescu, G., Lyonnard, D., Baghdadi, A., & Jerraya, A.-A. (avril 2001). A generic wrapper architecture for multi-processor SoC cosimulation and design [Communication écrite]. 9th international symposium on Hardware/software codesign (CODES 2021), Copenhagen, Denmark. Lien externe
