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Al-Akhras, S. I., Tahar, S., Nicolescu, G., Langevin, M., & Paulin, P. (2012, December). On the verification of a WiMax design using symbolic simulation [Paper]. 4th International Symposium on Symbolic Computation in Software Science, Gammarth, Tunisia. Published in Electronic Proceedings in Theoretical Computer Science, 122. Available
Ben Cheikh, T. L., Nicolescu, G., Trajković, J., Bouchebaba, Y., & Paulin, P. (2014, June). Fast and accurate implementation of Canny edge detector on embedded many-core platform [Paper]. 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Trois-Rivieres, QC, Canada. External link
Bouchebaba, Y., Ozcan, A.-E., Paulin, P., & Nicolescu, G. (2010, June). MpAssign : a Framework for Solving the Many-Core Platform Mapping Problem [Paper]. 21st IEEE International Symposium on Rapid System Prototyping (RSP 2010), Fairfax, Virginia. Published in Journal of Software: Practice and Experience, 42(7). External link
Bouchebaba, Y., Paulin, P., & Nicolescu, G. (2012). MpAssign : a framework for solving the many-core platform mapping problem. In Design technology for heterogeneous embedded systems (pp. 197-221). External link
Bouchebaba, Y., Girodias, B., Nicolescu, G., Aboulhamid, E. M., Lavigueur, B., & Paulin, P. (2007). MPSoC memory optimization using program transformation. ACM Transactions on Design Automation of Electronic Systems, 12(4), 43-43. External link
Deslauriers, F., Langevin, M., Bois, G., Savaria, Y., & Paulin, P. (2006, June). RoC: a scalable network on chip based on the token ring concept [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link
Girodias, B., Iugan, L. G., Bouchebaba, Y., Nicolescu, G., Abouhamid, E. M., Langevin, M., & Paulin, P. (2012). Integrating memory optimization with mapping algorithms for multi-processors system-on-chip. Transactions on Embedded Computing Systems, 11(3), 1-26. External link
Girodias, B., Gheorghe, L., Bouchebaba, Y., Nicolescu, G., Aboulhamid, E. M., Langevin, M., & Paulin, P. (2010, June). Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip [Paper]. 21st IEEE International Symposium on Rapid System Prototyping (RSP 2010), Fairfax, VA, USA. External link
Girodias, B., Bouchebaba, Y., Nicolescu, G., Aboulhamid, E. M., Paulin, P., & Lavigueur, B. (2006, June). Application-level memory optimization for MPSoC [Paper]. 17th IEEE International Workshop on Rapid System Prototyping, Chania, Crete, Greece. External link
Hadjiat, K., St-Pierre, F., Bois, G., Savaria, Y., Langevin, M., & Paulin, P. (2007, December). An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept [Paper]. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco. External link
Le Beux, S., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2013). Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocessors and Microsystems, 37(1), 87-98. External link
Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2011, March). Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology [Paper]. 14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France. External link
Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2010). Multi-optical network-on-chip for large scale MPSoC. IEEE Embedded Systems Letters, 2(3), 77-80. External link
Le Beux, S., Nicolescu, G., Bois, G., & Paulin, P. (2010, May). A system-level exploration flow for optical network on chip (ONoC) in 3D MPSoC [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. External link
Le Beux, S., Nicolescu, G., Bois, G., Bouchebaba, Y., Langevin, M., & Paulin, P. (2009, July). Optimizing configuration and application mapping for MPSoC architectures [Paper]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2009), San Francisco, California. External link
