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Nsame, P., Bois, G., & Savaria, Y. (2015, May). Analysis and characterization of data energy tradeoffs: for VLSI architectural agility in C-RAN platforms [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal. External link
Nsame, P., & Savaria, Y. (2004, July). A customizable embedded SoC platform architecture [Paper]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. External link
Nsame, P., & Savaria, Y. (2004, September). Multi-processor SoC integration: a case study on BlueGene [Paper]. IEEE International SOC Conference (SOCC 2004). External link
Nsame, P., & Savaria, Y. (2003, January). System-level design closure [Paper]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Unavailable
Nsame, P., Grou-Szabo, R., & Savaria, Y. (2000, January). INTIME: a multi-tool specification environment for ensuring timing constraints integrity for SOC design [Paper]. IP Based Design 2000, Grenoble, France. External link
Nsame, P., & Savaria, Y. (1999, January). Virtualising on-chip bus interfaces for improved embedded processor system performance [Paper]. IFIP International Workshop on IP Based Synthesis and System Design, Grenoble, France. Unavailable
