 | Up a level |
Hasan, S. R., Landry, A., Savaria, Y., & Nekili, M. (2004, June). Design constraints of hypertransport-compatible networks-on-chip [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link
Landry, A., Savaria, Y., & Nekili, M. (2005, June). Circuits techniques for a 2 GHz AMBA AHB Bus [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, Canada. External link
Landry, A., Nekili, M., & Savaria, Y. (2005, May). A novel 2 GHz Mulit-layer AMBA high-Speed bus interconnect matrix for SoC platforms [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Japon. External link
Landry, A., Savaria, Y., & Nekili, M. (2004, December). A beyond-1 GHz high-speed bus for SoC DSP platforms [Paper]. 16th International Conference on Microelectronics (ICM 2004), Tunisie. External link
Nekili, M., Savaria, Y., & Bois, G. (2001, May). Minimizing process-induced skew using elay tuning [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie. External link
Nekili, M., Savaria, Y., & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84. External link
Nekili, M., Savaria, Y., Bois, G., Bayoumi, M. A., & Jullien, G. (1998, February). Design of clock distribution networks in presence of process variations [Paper]. 8th Great Lakes Symposium on VLSI, Lafayette, LA, USA. External link
Nekili, M., Savaria, Y., & Bois, G. (1994, January). Fast low-power driver for long interconnections in VLSI systems [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), Londres. External link
Nekili, M., Savaria, Y., & Bois, G. (1994, August). A variable-size parallel regenerator for long integrated interconnections [Paper]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. External link
