Documents dont l'auteur est "Mashreghi-Moghadamy, Parisa"

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Mashreghi-Moghadamy, P., Ould-Bachir, T., & Savaria, Y. (mai 2022). A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA. Lien externe