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Kermouche, R., Audet, D., & Savaria, Y. (1995). On the optimization of integrated hierarchical bus architectures to achieve efficient fault-tolerance. Journal of Microelectronic Systems Integration, 3(1), 47-63. Non disponible
Kermouche, R., Savaria, Y., & Audet, D. (janvier 1994). Harvest model of an integrated hierarchical-bus architecture [Communication écrite]. 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, CA, USA. Lien externe