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Gao, S., Al-Khalili, D., Chabini, N., & Langlois, J. M. P. (2012). Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Computers and Digital Techniques, 6(6), 372-83. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2007, July). FPGA-based efficient design approach for large-size two's complement squarers [Paper]. IEEE International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2007). Optimised Realisations of Large Integer Multipliers and Squarers Using Embedded Blocks. IET Computers and Digital Techniques, 1(1), 9-16. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, September). Efficient FPGA-based realization of complex squarer and complex conjugate using embedded mulitpliers [Paper]. IEEE International SOC Conference (SOCC 2006), Austin, TX, USA. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, June). Efficient realization of large integers multipliers and squarers [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, March). An optimized design approach for squaring large integers using embedded hardwired multipliers [Paper]. ACS/IEEE International Conference on Computer Systems and Applications. External link
