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Gao, S., Al-Khalili, D., Chabini, N., & Langlois, J. M. P. (2012). Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Computers and Digital Techniques, 6(6), 372-83. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2007, July). FPGA-based efficient design approach for large-size two's complement squarers [Paper]. IEEE International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2007). Optimised Realisations of Large Integer Multipliers and Squarers Using Embedded Blocks. IET Computers and Digital Techniques, 1(1), 9-16. External link
Langlois, J. M. P., & Al-Khalili, D. (2006). Carry-free approximate squaring functions with O(n) complexity and O(1) delay. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(5), 374-378. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, September). Efficient FPGA-based realization of complex squarer and complex conjugate using embedded mulitpliers [Paper]. IEEE International SOC Conference (SOCC 2006). External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, June). Efficient realization of large integers multipliers and squarers [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, March). An optimized design approach for squaring large integers using embedded hardwired multipliers [Paper]. ACS/IEEE International Conference on Computer Systems and Applications. External link
Langlois, J. M. P., Al-Khalili, D., & Al-Hertani, H. '. (2004, June). Carry free, bit parallel approximate squarers with linear complexity and constant delay [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link
Langlois, J. M. P., & Al-Khalili, D. (2004). Phase to sinusoid amplitude conversion techniques for direct digital frequency synthesis. IEE Proceedings-Circuits, Devices and Systems, 151(6), 519-528. External link
Langlois, J. M. P., & Al-Khalili, D. (2003, September). Low power direct digital frequency synthesizers in 0.18 μm CMOS [Paper]. IEEE Custom Integrated Circuits Conference (CICC 2003), San José, CA, USA. External link
Langlois, J. M. P., & Al-Khalili, D. (2003, June). Piecewise continuous linear interpolation of the sine function for direct digital frequency synthesis [Paper]. IEEE MTT-S International Microwave Symposium (IMS 2003), Philadelphia, PA, USA. External link
Liu, Q., Langlois, J. M. P., Al-Khalili, D., Szwarc, V., & Ink, R. (2003, May). Synthesis of a 12-bit complex mixer for FPGA implementation [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003), Montréal, Québec. External link
Langlois, J. M. P., & Al-Khalili, D. (2002, May). A new approach to the design of low power direct digital frequency synthesizers [Paper]. IEEE International Frequency Control Symposium and PDA Exhibition, New Orleans, USA. External link
Langlois, J. M. P., & Al-Khalili, D. (2001, August). ROM size reduction with low processing cost for direct digital frequency synthesis [Paper]. IEEE Pacific Rim Conference on Communications, Computers and signal Processing (PACRIM 2001), Victoria, Canada. External link
Langlois, J. M. P., Al-Khalili, D., & Inkol, R. J. (1999, May). A high performance, wide bandwidth, low cost FPGA-based quadrature demodulator [Paper]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 1999), Edmonton, Canada. External link
