A low-power, low-noise recycling folded-cascode operational transconductance amplifier for neural recording applications

We present in this paper a low-noise, low-power CMOS operational transconductance amplifier designed for the preconditioning stage of implantable neural recording microsystems. The proposed single-stage amplifier utilizes a combination of recently published techniques, including cross-coupled devices in a recycling folded-cascode topology with positive feedback, to achieve high DC voltage gain and unity-gain bandwidth while minimizing power consumption. A mixed N-type and P-type MOSFET input stage enhances input common-mode performance. Designed and implemented in a 0.18-µm CMOS process with a 1.8 V supply, post-layout simulations demonstrate an open-loop voltage gain of 97.23 dB, a 2.91 MHz unity-gain bandwidth (with a 1 pF load), and an input-referred noise of 4.75 μVᵣₘₛ. The total power dissipation, including bias circuitry, is 5.43 μW, and the amplifier occupies a chip area of 0.0055 mm². Integrated into a conventional neural recording amplifier configuration, the proposed amplifier achieves a simulated input-referred noise of 5.73 µVᵣₘₛ over a 1 Hz to 10 kHz bandwidth with a power consumption of 5.6 µW. This performance makes it suitable for amplifying both action potential and local field potential signals. The amplifier provides an output voltage swing of 0.976 Vₚₚ with a total harmonic distortion of −62.68 dB at 1 kHz.

Mots clés

• implantable microsystem
• neural signals
• neural amplifiers
• low-power and low-noise operational amplifier
• recycling folded-cascode