Yield maximization of flip-flop circuits based on deep neural network and polyhedral estimation of nonlinear constraints

In this paper, we propose a method based on deep neural networks for the statistical design of flip-flops, taking into account nonlinear performance constraints. Flip-flop design and manufacturing are influenced by random variations in the technological process, making deterministic design approaches inadequate for achieving high yields. The conventional yield maximization method using Monte Carlo (MC) simulation is a time-consuming process. Also, for many performance constraints, either there are no analytical formulations or if they exist, they are not sufficiently accurate to be used in circuit optimization. To address these challenges, we approximated the nonlinear constraints with linearized ones (polyhedral approximation) and performed a yield maximization process which was done by developing our first proposed method. Then in the second proposed method, we used deep neural networks to generate precise nonlinear closed-form models for circuit performance metrics and also replaced MC simulation with an analytical yield formula. The combination of these techniques significantly enhances the speed and accuracy of statistical circuit design by employing powerful gradient-based optimization methods that converge quickly to the optimal solution. Experimental results demonstrate that our proposed approach enables the design of circuits with various performance constraints under process variation, and achieves more optimum results with much fewer iterations and less CPU time compared to the conventional simulation-based yield maximization methods.

Mots clés

computer-aided design (CAD); circuit yield maximization; circuit simulation; deep neural network (DNN); flip-flop circuits; gate sizing; nanometer regime technologies; process variations; statistical design.