The design and simulation of a 400/533Mbps DDR-II SDRAM memory interconnect bus

Mohammad S. Sharawi and M. T. Al-Qdah

Paper (2008)

Document published while its authors were not affiliated with Polytechnique Montréal

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PolyPublie URL:	https://publications.polymtl.ca/42102/
Conference Title:	5th International Multi-Conference on Systems, Signals and Devices
Conference Location:	Amman, Jordan
Conference Date(s):	2008-07-20 - 2008-07-22
Publisher:	IEEE
DOI:	10.1109/ssd.2008.4632797
Official URL:	https://doi.org/10.1109/ssd.2008.4632797
Date Deposited:	18 Apr 2023 15:16
Last Modified:	05 May 2023 15:46

Cite in APA 7:	Sharawi, M. S., & Al-Qdah, M. T. (2008, July). The design and simulation of a 400/533Mbps DDR-II SDRAM memory interconnect bus [Paper]. 5th International Multi-Conference on Systems, Signals and Devices, Amman, Jordan (6 pages). https://doi.org/10.1109/ssd.2008.4632797
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