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Hardware-assisted instruction profiling and latency detection

Suchakrapani Datt Sharma and Michel Dagenais

Article (2016)

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Debugging and profiling tools can alter the execution flow or timing, can induce heisenbugs and are thus marginally useful for debugging time critical systems. Software tracing, however advanced it may be, depends on consuming precious computing resources. In this study, the authors analyse state-of-the-art hardware-tracing support, as provided in modern Intel processors and propose a new technique which uses the processor hardware for tracing without any code instrumentation or tracepoints. They demonstrate the utility of their approach with contributions in three areas - syscall latency profiling, instruction profiling and software-tracer impact detection. They present improvements in performance and the granularity of data gathered with hardware-assisted approach, as compared with traditional software only tracing and profiling. The performance impact on the target system – measured as time overhead – is on average 2–3%, with the worst case being 22%. They also define a way to measure and quantify the time resolution provided by hardware tracers for trace events, and observe the effect of finetuning hardware tracing for optimum utilisation. As compared with other in-kernel tracers, they observed that hardware-based tracing has a much reduced overhead, while achieving greater precision. Moreover, the other tracing techniques are ineffective in certain tracing scenarios.

Uncontrolled Keywords

program debugging, program diagnostics, latency detection, syscall latency profiling, fine-tuning hardware tracing, hardware-assisted instruction profiling, hardware-based tracing, software tracing, sixth generation Intel processors, optimum utilisation, programming support Diagnostic testing, debugging and evaluating systems

Subjects: 2700 Information technology > 2700 Information technology
2700 Information technology > 2715 Optimization
Department: Department of Computer Engineering and Software Engineering
Funders: CRSNG/NSERC, Ericsson Software Research, EfficiOS, Prompt
PolyPublie URL: https://publications.polymtl.ca/3068/
Journal Title: The Journal of Engineering (vol. 2016, no. 10)
Publisher: IET
DOI: 10.1049/joe.2016.0127
Official URL: https://doi.org/10.1049/joe.2016.0127
Date Deposited: 04 May 2018 16:18
Last Modified: 15 May 2023 15:48
Cite in APA 7: Sharma, S. D., & Dagenais, M. (2016). Hardware-assisted instruction profiling and latency detection. The Journal of Engineering, 2016(10), 367-376. https://doi.org/10.1049/joe.2016.0127


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