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Bois, G., Moss, L., Filion, L., & Fontaine, S. (2010). Codesign experiences based on a virtual platform. Dans Bailey, B., & Martin, G. (édit.), ESL models and their application : electronic system level design and verification practice (273-309). Lien externe
Le Beux, S., Bois, G., Nicolescu, G., Bouchebaba, Y., Langevin, M., & Paulin, P. (2010). Combining mapping and partitioning exploration for NoC-based embedded systems. Journal of Systems Architecture, 56(7), 223-232. Lien externe
Le Beux, S., Nicolescu, G., Bois, G., & Paulin, P. (mai 2010). A system-level exploration flow for optical network on chip (ONoC) in 3D MPSoC [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. Lien externe
Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2010). Multi-optical network-on-chip for large scale MPSoC. IEEE Embedded Systems Letters, 2(3), 77-80. Lien externe
Rogers-Vallée, M., Cantin, M.-A., Moss, L., & Bois, G. (octobre 2010). IP characterization methodology for fast and accurate power consumption estimation at transactional level model [Communication écrite]. IEEE International Conference on Computer Design (ICCD 2010), Amsterdam, Netherlands. Lien externe
