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David, J. P., & Bergeron, E. (septembre 2004). An intermediate level HDL for system level design [Communication écrite]. 7th Forum on Specification and Design Languages (FDL 2004), Lille, France. Non disponible
David, J. P., & Bergeron, E. (juillet 2004). A step towards intelligent translation from high-level design to RTL [Communication écrite]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2004), Banff, Canada. Lien externe
Lapalme, J., Aboulhamed, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (juin 2004). Esys.net: A New Solution for Embedded Systems Modeling and Simulation [Communication écrite]. ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, D.C.. Publié dans ACM Sigplan Notices, 39(7). Lien externe
Lapalme, J., Aboulhamid, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (février 2004). [dot]Net framework - A solution for the next generation tools for system-level modeling and simulation [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France. Lien externe
Ogoubi, E., & David, J. P. (juin 2004). Automatic synthesis from high level ASM to VHDL: a case study [Communication écrite]. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Zerarka, M. T., David, J. P., & Aboulhamid, E. M. (juillet 2004). High speed emulation of gene regulatory networks using FPGAs [Communication écrite]. 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japan. Lien externe
