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Beaudin, S., Marceau, R. J., Bois, G., Savaria, Y., & Kandil, N. (2003). An Economic Parallel Processing Technology for Faster Than Real-Time Transient Stability Simulation. European Transactions on Electrical Power, 13(2), 105-112. Lien externe
Bertola, M., & Bois, G. (septembre 2003). A methodology for the design of AHB bus master wrappers [Communication écrite]. Euromicro Symposium on Digital System Design. Lien externe
Bertola, M., & Bois, G. Teaching Bus Architectures With a Basic, Hands-on Soc Platform [Communication écrite]. IEEE International Conference on Microelectronic Systems Education (MSE 2003). Lien externe
Bissou, J. P., Dubois, M., Savaria, Y., & Bois, G. (décembre 2003). High-speed system bus for a SoC network processing platform [Communication écrite]. 15th International Conference on Microelectronics (ICM 2003), Cairo, Egypt. Lien externe
Charest, L., Aboulhamid, M., & Bois, G. (2003). Applying multi-paradigm and patterns approaches to hardware/software design and reuse. Dans Patterns and skeletons for parallel and distributed computing (p. 97-325). Lien externe
Filion, L., Chevalier, J., Bois, G., & Aboulhamid, E. M. The Syslib-Picasso Methodology for the Co-Design Specification Capture Phase [Communication écrite]. System-on-Chip for Real-Time Applications. Lien externe
Lemire, J. F., Aboulhamid, E. M., Savaria, Y., Bois, G., & Baron, A. (février 2003). Implementing e assertion checkers from an SDL executable specifications [Communication écrite]. DVCON, San José, USA. Non disponible
Regimbal, S., Lemire, J. F., Savaria, Y., Bois, G., Aboulhamid, M., & Baron, A. (juillet 2002). Aspect Partitioning for Hardware Verification Reuse [Communication écrite]. System-on-Chip for Real-Time Applications. Lien externe
Regimbal, S., Lemire, J.-F., Savaria, Y., Bois, G., Aboulhamid, E. M., & Baron, A. (juin 2003). Automating functional coverage analysis based on an executable specification [Communication écrite]. 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications. Lien externe