Items where Author is "Paulin, P."

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Deslauriers, F., Langevin, M., Bois, G., Savaria, Y., & Paulin, P. (2006, June). RoC: a scalable network on chip based on the token ring concept [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link

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Girodias, B., Gheorghe, L., Bouchebaba, Y., Nicolescu, G., Aboulhamid, E. M., Langevin, M., & Paulin, P. (2010, June). Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip [Paper]. 21st IEEE International Symposium on Rapid System Prototyping (RSP 2010), Fairfax, VA, USA. External link

Girodias, B., Bouchebaba, Y., Nicolescu, G., Aboulhamid, E. M., Paulin, P., & Lavigueur, B. (2009). Multiprocessor, multithreading and memory optimization for on-chip multimedia applications. Journal of Signal Processing Systems, 57(2), 263-283. External link

Girodias, B., Bouchebaba, Y., Nicolescu, G., Aboulhamid, E. M., Paulin, P., & Lavigueur, B. (2006, June). Application-level memory optimization for MPSoC [Paper]. 17th IEEE International Workshop on Rapid System Prototyping, Chania, Crete, Greece. External link

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Hadjiat, K., St-Pierre, F., Bois, G., Savaria, Y., Langevin, M., & Paulin, P. (2007, December). An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept [Paper]. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco. External link

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Le Beux, S., Bois, G., Nicolescu, G., Bouchebaba, Y., Langevin, M., & Paulin, P. (2010). Combining mapping and partitioning exploration for NoC-based embedded systems. Journal of Systems Architecture, 56(7), 223-232. External link

Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2010). Multi-optical network-on-chip for large scale MPSoC. IEEE Embedded Systems Letters, 2(3), 77-80. External link

Le Beux, S., Nicolescu, G., Bois, G., & Paulin, P. (2010, May). A system-level exploration flow for optical network on chip (ONoC) in 3D MPSoC [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. External link

Le Beux, S., Nicolescu, G., Bois, G., Bouchebaba, Y., Langevin, M., & Paulin, P. (2009, July). Optimizing configuration and application mapping for MPSoC architectures [Paper]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2009), San Francisco, California. External link