 | Monter d'un niveau |
Khali, H., Savaria, Y., & Houle, J.-L. (2005). A system level implementation strategy and partitioning algorithm for applications based on lookup tables. International Journal of Computer and Electrical Engineering, 31(7), 485-502. Lien externe
Khali, H., & Savaria, Y. (décembre 2003). Hardware-software co design model for real-time 3D image computation using active laser range finders : a case study [Communication écrite]. 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2003), Sharjah, United Arab Emirates. Lien externe
Khali, H., Savaria, Y., Houle, J. L., Rioux, M., Beraldin, J. A., & Poussart, D. (2003). Improvement of Sensor Accuracy in the Case of a Variable Surface Reflectance Gradient for Active Laser Range Finders. IEEE Transactions on Instrumentation and Measurement, 52(6), 1799-1808. Lien externe
Khali, H., Savaria, Y., & Houle, J.-L. (juillet 1997). Computational limits of homogeneous acceleration using lookup tables [Communication écrite]. 11th Annual International Symposium on High Performance Computing Systems, Winnipeg, Man., Canada. Non disponible
Khali, H., & Houle, J.-L. (mai 1993). Vector and parallel implementation of algorithms and architectures for wavelet transforms [Communication écrite]. Eleventh IASTED International Conference Applied Informatics, Annecy, France. Non disponible
Khali, H., Savaria, Y., Houle, J.-L., Beraldin, J. A., Blais, F., & Rioux, M. (septembre 1995). VLSI chip for 3-D camera calibration [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montréal, Québec. Lien externe
Lebegue, F., Khali, H., & Houle, J.-L. (octobre 1994). Wavelet transform implementations on parallel digital signal processors [Communication écrite]. 6th IASTED/ISMM International Conference. Parallel and Distributed Computing and Systems, Washington, DC, USA. Non disponible
Savaria, Y., El Hassan, F., Khali, H., & Sawan, M. (janvier 1998). Effective hardware/software implementation of a viterbi decoder using an FPGA-based reconfigurable computing platform [Communication écrite]. FDP 1998. Non disponible
