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Bergeron, E., Feeley, M., Daigneault, M.-A., & David, J. P. (juin 2008). Using dynamic reconfiguration to implement high-resolution programmable Delays on an FPGA [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec. Lien externe
Daigneault, M.-A., & David, J. P. (2018). Automated synthesis of streaming transfer level hardware designs. ACM Transactions on Reconfigurable Technology and Systems, 11(2), 1-22. Lien externe
Daigneault, M.-A., & David, J. P. (mai 2015). Intermediate-level synthesis of a Gauss-Jordan elimination linear solver [Communication écrite]. 29th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015), Hyderabad, India. Lien externe
Daigneault, M.-A., & David, J. P. (2014). Fast description and synthesis of control-dominant circuits. Computers and Electrical Engineering, 40(4), 1199-1214. Lien externe
Daigneault, M.-A., & David, J. P. (avril 2013). High-level description and synthesis of floating-point accumulators on FPGA [Communication écrite]. 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Seattle, WA, United states. Lien externe
Daigneault, M.-A., & David, J. P. (août 2012). Raising the abstraction level of HDL for control-dominant applications [Communication écrite]. 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), Oslo, Norway. Lien externe
Daigneault, M.-A., & David, J. P. (2011). A high-resolution time-to-digital converter on FPGA using dynamic reconfiguration. IEEE Transactions on Instrumentation and Measurement, 60(6), 2070-2079. Lien externe
